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AllocationConstraint

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pub(all) enum AllocationConstraint {
  AnyReg
  AnyLocation
  PreservedHome
  FixedReg(PhysicalReg)
} derive(Eq, 
Debug)

A normalized register-allocation constraint.

Operand ties are represented separately by a shared nonnegative tie label, so this type contains only location constraints.

AllocationConstraint::equal

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AllocationConstraint::not_equal

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AllocationConstraint::to_repr

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AllocationLocation

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pub(all) struct AllocationLocation {
  encoded : Int64
} derive(Eq)

A packed allocation result location within one allocation session.

Spill indices are session-local and must be translated at ownership boundaries before they are exposed as product-facing stack-slot handles.

AllocationLocation::equal

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AllocationLocation::is_register

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fn AllocationLocation::is_register(self : AllocationLocation) -> Bool

AllocationLocation::is_spill

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fn AllocationLocation::is_spill(self : AllocationLocation) -> Bool

AllocationLocation::not_equal

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AllocationLocation::reg

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AllocationLocation::register

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AllocationLocation::register_unchecked

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fn AllocationLocation::register_unchecked(self : AllocationLocation) -> PhysicalReg

Decode a register location after is_register has been established.

AllocationLocation::spill

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fn AllocationLocation::spill(index : Int) -> AllocationLocation

AllocationLocation::spill_index

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fn AllocationLocation::spill_index(self : AllocationLocation) -> Int?

AllocationLocation::spill_index_unchecked

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fn AllocationLocation::spill_index_unchecked(self : AllocationLocation) -> Int

Decode a spill location after is_spill has been established.

AllocationLocation::to_repr

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AllocationOperand

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pub(all) struct AllocationOperand {
  vreg : VirtualReg
  role : OperandRole
  constraint : AllocationConstraint
  preference : PhysicalReg?
  tie_id : Int
  timing : OperandTiming
} derive(Eq, 
Debug)

The canonical allocation facts for one instruction operand.

AllocationOperand::def

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AllocationOperand::equal

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AllocationOperand::not_equal

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fn AllocationOperand::not_equal(x : AllocationOperand, y : AllocationOperand) -> Bool

AllocationOperand::to_repr

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AllocationOperand::use_reg

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AllocationOperand::with_constraint

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fn AllocationOperand::with_constraint(self : AllocationOperand, constraint : AllocationConstraint) -> AllocationOperand

AllocationOperand::with_preference

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fn AllocationOperand::with_preference(self : AllocationOperand, preference : PhysicalReg) -> AllocationOperand

Prefer a physical register without making it a correctness constraint.

AllocationOperand::with_tie

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fn AllocationOperand::with_tie(self : AllocationOperand, tie_id : Int) -> AllocationOperand

Tie operands in one instruction by a shared nonnegative label.

AllocationOperand::with_timing

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OperandRole

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pub(all) enum OperandRole {
  Use
  Def
  UseDef
} derive(Eq, 
Debug)

Whether an allocation operand reads, writes, or both reads and writes its virtual register.

SSA VCode producers use Use and Def. UseDef remains available to standalone register-allocation clients that model in-place updates.

OperandRole::equal

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fn OperandRole::equal(OperandRole, OperandRole) -> Bool

OperandRole::not_equal

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fn OperandRole::not_equal(x : OperandRole, y : OperandRole) -> Bool

OperandRole::to_repr

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OperandTiming

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pub(all) enum OperandTiming {
  Early
  Late
} derive(Eq, 
Debug)

The point within an instruction where an allocation operand is read or written.

OperandTiming::equal

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OperandTiming::not_equal

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fn OperandTiming::not_equal(x : OperandTiming, y : OperandTiming) -> Bool

OperandTiming::to_repr

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PhysicalReg

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pub(all) struct PhysicalReg {
  id : Int
  class : RegClass
} derive(Eq)

A target physical register identified within one register class.

PhysicalReg::equal

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fn PhysicalReg::equal(PhysicalReg, PhysicalReg) -> Bool

PhysicalReg::new

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fn PhysicalReg::new(id : Int, class : RegClass) -> PhysicalReg

PhysicalReg::not_equal

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fn PhysicalReg::not_equal(x : PhysicalReg, y : PhysicalReg) -> Bool

PhysicalReg::to_repr

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RegClass

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pub(all) enum RegClass {
  Int
  Float
  Vector
  FpVector
} derive(Eq, Hash, 
Debug)

Target-neutral register-class identity shared by VCode and register allocation.

FpVector preserves targets whose scalar floating-point and vector values occupy one physical register bank. Float and Vector remain available to standalone allocator embeddings that model distinct banks.

RegClass::equal

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fn RegClass::equal(RegClass, RegClass) -> Bool

RegClass::hash

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fn RegClass::hash(self : RegClass) -> Int

RegClass::hash_combine

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fn RegClass::hash_combine(RegClass, Hasher) -> Unit

RegClass::not_equal

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fn RegClass::not_equal(x : RegClass, y : RegClass) -> Bool

RegClass::text

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fn RegClass::text(self : RegClass) -> String

RegClass::to_repr

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VirtualReg

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pub(all) struct VirtualReg {
  id : Int
  class : RegClass
} derive(Eq, 
Debug)

A dense virtual-register identity within one allocation session.

VirtualReg::equal

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fn VirtualReg::equal(VirtualReg, VirtualReg) -> Bool

VirtualReg::not_equal

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fn VirtualReg::not_equal(x : VirtualReg, y : VirtualReg) -> Bool

VirtualReg::to_repr

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