🥮 mooncakes.io
    Sign in

    Milky2018/machv/instr does not have a README file

    CallClobberClass

    source
    pub(all) enum CallClobberClass {
      Internal
      Foreign
    } derive(Eq, 
    Debug    )

    Call-site clobber class for register allocation and optimization barriers.

    CallType

    source
    pub(all) enum CallType {
      None
      Regular
      TailCall
    }

    Call type - classifies instructions that behave like calls CallType enum for different call variants

    CmpKind

    source
    pub(all) enum CmpKind {
      Eq
      Ne
      Slt
      Sle
      Sgt
      Sge
      Ult
      Ule
      Ugt
      Uge
    }

    Comparison kind for integer comparisons
    impl Show for CmpKind

    CodeSymbol

    source
    pub(all) struct CodeSymbol {
      scope : String
      ordinal : Int
    } derive(Eq, Hash, 
    Debug    )

    Symbolic name for code owned by the embedding.

    MachV treats this as an opaque relocation key. Frontends may use the scope and ordinal to map their own function identifiers to this generic code target without exposing those identifiers in MachV opcodes.
    impl Show for CodeSymbol

    CodeSymbol::CodeSymbol

    source
    fn CodeSymbol::CodeSymbol(scope : String, ordinal : Int) -> CodeSymbol

    Cond

    source
    pub(all) enum Cond {
      Eq
      Ne
      Hs
      Lo
      Mi
      Pl
      Vs
      Vc
      Ps
      Pc
      Hi
      Ls
      Ge
      Lt
      Gt
      Le
      Al
    }

    AArch64 condition codes (for conditional branches and traps) Condition codes for comparisons
    impl Show for Cond

    Cond::invert

    source
    fn Cond::invert(self : Cond) -> Cond

    Invert condition code (for branch inversion optimization) E.g., Eq -> Ne, Hs -> Lo, Ge -> Lt

    Cond::to_bits

    source
    fn Cond::to_bits(self : Cond) -> Int

    Get the condition code value for AArch64 encoding

    ExtendKind

    source
    pub(all) enum ExtendKind {
      Signed8To32
      Signed8To64
      Signed16To32
      Signed16To64
      Signed32To64
      Unsigned8To32
      Unsigned8To64
      Unsigned16To32
      Unsigned16To64
      Unsigned32To64
    }

    Extend kind - how to extend a value
    impl Show for ExtendKind

    ExternalName

    source
    pub(all) struct ExternalName {
      name : String
    } derive(Eq, Hash, 
    Debug    )

    Symbolic name for a runtime or external helper address.

    MachV treats this as an opaque relocation key. Embedding packages own the mapping from names to native addresses.

    ExternalName::ExternalName

    source
    fn ExternalName::ExternalName(name : String) -> ExternalName

    FCmpKind

    source
    pub(all) enum FCmpKind {
      Eq
      Ne
      Lt
      Le
      Gt
      Ge
    }

    Comparison kind for float comparisons
    impl Show for FCmpKind

    FloatToIntKind

    source
    pub(all) enum FloatToIntKind {
      F32ToI32S
      F32ToI32U
      F32ToI64S
      F32ToI64U
      F64ToI32S
      F64ToI32U
      F64ToI64S
      F64ToI64U
      F32ToI32SSat
      F32ToI32USat
      F32ToI64SSat
      F32ToI64USat
      F64ToI32SSat
      F64ToI32USat
      F64ToI64SSat
      F64ToI64USat
    }

    Float to Int conversion kind Encodes: source float type, destination int type, signedness

    IndexExtend

    source
    pub(all) enum IndexExtend {
      None
      Uxtw
      Sxtw
    }

    AArch64 addressing-mode extend for register-offset loads/stores.

    Mirrors Cranelift's AMode.{RegExtended,RegScaledExtended} options:
    • None: use X register offset (LSL option)
    • Uxtw/Sxtw: extend Wm to X, optionally scaled by access size (S bit)
    impl Show for IndexExtend

    Inst

    source

    MachV instruction - a machine-level instruction with virtual registers Operand constraints for fixed register allocation
    impl Show for Inst

    Inst::Inst

    source
    fn Inst::Inst(opcode : Opcode) -> Inst

    Inst::add_def

    source
    fn Inst::add_def(self : Inst, reg : 
    Writable    ) -> Unit

    Inst::add_def_fixed

    source
    fn Inst::add_def_fixed(self : Inst, reg : 
    Writable    , preg : 
    PReg    ) -> Unit

    Add a def operand with a fixed register constraint

    Inst::add_use

    source
    fn Inst::add_use(self : Inst, reg : 
    Reg    ) -> Unit

    Inst::add_use_fixed

    source
    fn Inst::add_use_fixed(self : Inst, reg : 
    Reg    , preg : 
    PReg    ) -> Unit

    Add a use operand with a fixed register constraint

    IntToFloatKind

    source
    pub(all) enum IntToFloatKind {
      I32SToF32
      I32UToF32
      I64SToF32
      I64UToF32
      I32SToF64
      I32UToF64
      I64SToF64
      I64UToF64
    }

    Int to Float conversion kind Encodes: source int type, destination float type, signedness

    LaneSize

    source
    pub(all) enum LaneSize {
      B8
      H16
      S32
      D64
    }

    SIMD lane size for vector operations
    impl Show for LaneSize

    MemType

    source
    pub(all) enum MemType {
      I32
      I64
      F32
      F64
      V128
    }

    Memory type for load/store
    impl Show for MemType

    Opcode

    source
    pub(all) enum Opcode {
      Add(Bool)
      AddImm(Int, Bool)
      Sub(Bool)
      SubImm(Int, Bool)
      Mul(Bool)
      SDiv(Bool)
      UDiv(Bool)
      SRem(Bool)
      URem(Bool)
      And(Bool)
      AndImm(Int64, Bool)
      Or(Bool)
      OrImm(Int64, Bool)
      Xor(Bool)
      XorImm(Int64, Bool)
      Shl(Bool)
      ShlImm(Int, Bool)
      AShr(Bool)
      AShrImm(Int, Bool)
      LShr(Bool)
      LShrImm(Int, Bool)
      Rotr(Bool)
      RotrImm(Int, Bool)
      ExtrImm(Int, Bool)
      Not(Bool)
      AndNot(Bool)
      OrNot(Bool)
      XorNot(Bool)
      FAdd(Bool)
      FSub(Bool)
      FMul(Bool)
      FDiv(Bool)
      FMin(Bool)
      FMax(Bool)
      FSqrt(Bool)
      FAbs(Bool)
      FNeg(Bool)
      FCeil(Bool)
      FFloor(Bool)
      FTrunc(Bool)
      FNearest(Bool)
      Load(MemType, Int)
      Store(MemType, Int)
      Load8S(Int)
      Load8U(Int)
      Load16S(Int)
      Load16U(Int)
      Load32S(Int)
      Load32U(Int)
      Move
      LoadConst(Int64)
      LoadConstF32(Int)
      LoadConstF64(Int64)
      Cmp(CmpKind, Bool)
      IntCmp(Bool)
      FCmp(FCmpKind)
      Extend(ExtendKind)
      Truncate
      IntToFloat(IntToFloatKind)
      FPromote
      FDemote
      Bitcast
      Select
      SelectCmp(CmpKind, Bool)
      Clz(Bool)
      Popcnt(Bool)
      Rbit(Bool)
      Nop
      TrapIfUgt(Int)
      TrapIfUge(Int)
      FpuCmp(Bool)
      TrapIf(Cond, Int)
      TrapIfZero(Bool, Int)
      TrapIfDivOverflow(Bool, Int)
      FcvtToInt(Bool, Bool, Bool)
      FpuSel(Bool, Cond)
      FpuMaxnm(Bool)
      FpuMinnm(Bool)
      AddShifted(ShiftType, Int)
      AddExtend(IndexExtend, Int)
      SubExtend(IndexExtend, Int)
      SubShifted(ShiftType, Int)
      AndShifted(ShiftType, Int)
      OrShifted(ShiftType, Int)
      XorShifted(ShiftType, Int)
      AddShifted32(ShiftType, Int)
      SubShifted32(ShiftType, Int)
      AndShifted32(ShiftType, Int)
      OrShifted32(ShiftType, Int)
      XorShifted32(ShiftType, Int)
      Madd
      Msub
      Mneg
      Madd32
      Msub32
      Mneg32
      Umulh
      Smulh
      Umull
      Smull
      ReturnCallIndirect(Int, Int)
      CallExternalIfI32NeImm(Int, ExternalName)
      StackLoad(Int)
      StackStore(Int)
      LoadStackParam(Int, 
    RegClass    )
      LoadPtr(MemType, Int)
      LoadPtrRegOffset(MemType, IndexExtend, Int, Int)
      LoadPtrNarrowRegOffset(Int, Bool, IndexExtend, Int, Int)
      StorePtr(MemType, Int)
      StorePtrRegOffset(MemType, IndexExtend, Int, Int)
      StorePtrNarrowRegOffset(Int, IndexExtend, Int, Int)
      LoadPtrNarrow(Int, Bool, Int)
      StorePtrNarrow(Int, Int)
      LoadExternalFuncAddr(ExternalName)
      LoadCodeAddr(CodeSymbol)
      CallPtr(Int, Array[
    RegClass    ], CallClobberClass)
      CallDirect(CodeSymbol, Int, Array[
    RegClass    ], CallClobberClass)
      CallExternal(ExternalName, Int, Array[
    RegClass    ], CallClobberClass)
      AdjustSP(Int)
      StoreToStack(Int)
      LoadSP
      LoadSafepointId(Int)
      LoadConstV128(Bytes)
      SIMDSplat(LaneSize)
      SIMDSplatF(Bool)
      SIMDExtractU(LaneSize, Int)
      SIMDExtractS(LaneSize, Int)
      SIMDExtractF(Bool, Int)
      SIMDInsert(LaneSize, Int)
      SIMDInsertF(Bool, Int)
      SIMDShuffle(FixedArray[Int])
      SIMDSwizzle
      SIMDNot
      SIMDAnd
      SIMDBic
      SIMDOr
      SIMDXor
      SIMDBsl
      SIMDAnyTrue
      SIMDAllTrue(LaneSize)
      SIMDBitmask(LaneSize)
      SIMDAdd(LaneSize)
      SIMDSub(LaneSize)
      SIMDMul(LaneSize)
      SIMDSqadd(LaneSize)
      SIMDUqadd(LaneSize)
      SIMDSqsub(LaneSize)
      SIMDUqsub(LaneSize)
      SIMDSmin(LaneSize)
      SIMDUmin(LaneSize)
      SIMDSmax(LaneSize)
      SIMDUmax(LaneSize)
      SIMDUrhadd(LaneSize)
      SIMDAbs(LaneSize)
      SIMDNeg(LaneSize)
      SIMDCnt
      SIMDBroadcastShift(LaneSize, Bool)
      SIMDShiftByVec(LaneSize, Bool)
      SIMDCmp(LaneSize, SIMDCmpKind)
      SIMDNarrow(LaneSize, Bool)
      SIMDExtendLow(LaneSize, Bool)
      SIMDExtendHigh(LaneSize, Bool)
      SIMDExtMulLow(LaneSize, Bool)
      SIMDExtMulHigh(LaneSize, Bool)
      SIMDExtAddPairwise(LaneSize, Bool)
      SIMDDot
      SIMDQ15MulrSat
      SIMDFAdd(Bool)
      SIMDFSub(Bool)
      SIMDFMul(Bool)
      SIMDFDiv(Bool)
      SIMDFMin(Bool)
      SIMDFMax(Bool)
      SIMDFPMin(Bool)
      SIMDFPMax(Bool)
      SIMDFAbs(Bool)
      SIMDFNeg(Bool)
      SIMDFSqrt(Bool)
      SIMDFCeil(Bool)
      SIMDFFloor(Bool)
      SIMDFTrunc(Bool)
      SIMDFNearest(Bool)
      SIMDFCmp(Bool, SIMDFCmpKind)
      SIMDFCvtToIntS(Bool)
      SIMDFCvtToIntU(Bool)
      SIMDIntToFloatS(Bool)
      SIMDIntToFloatU(Bool)
      SIMDTruncSatF64ToI32SZero
      SIMDTruncSatF64ToI32UZero
      SIMDConvertLowI32ToF64S
      SIMDConvertLowI32ToF64U
      SIMDDemoteF64ToF32Zero
      SIMDPromoteLowF32ToF64
      SIMDLoad(Int)
      SIMDStore(Int)
      SIMDLoadSplat(LaneSize, Int)
      SIMDLoadExtend(Int, Bool, Int)
      SIMDLoadZero(Bool, Int)
      SIMDLoadLane(LaneSize, Int, Int)
      SIMDStoreLane(LaneSize, Int, Int)
      SIMDFMla(Bool)
      SIMDFMls(Bool)
      SIMDRelaxedDot8to16
      SIMDRelaxedDot8to32Add
    }

    MachV opcode - machine-level operation (target-independent subset)
    impl Show for Opcode

    Opcode::call_result_classes

    source
    fn Opcode::call_result_classes(self : Opcode) -> Array[
    RegClass    ]?

    Opcode::call_result_count

    source
    fn Opcode::call_result_count(self : Opcode) -> Int?

    Opcode::call_type

    source
    fn Opcode::call_type(self : Opcode) -> CallType

    Get the call type for this opcode Design: instructions that clobber caller-saved registers are classified as calls for register allocation purposes

    RelocTarget

    source
    pub(all) enum RelocTarget {
      Code(CodeSymbol)
      External(ExternalName)
    } derive(Eq, 
    Debug    )

    Target for a relocatable code address or direct call.
    impl Show for RelocTarget

    RelocTarget::key

    source
    fn RelocTarget::key(self : RelocTarget) -> String

    SIMDCmpKind

    source
    pub(all) enum SIMDCmpKind {
      Eq
      GtS
      GeS
      GtU
      GeU
    }

    SIMD comparison kind for integer vector comparisons
    impl Show for SIMDCmpKind

    SIMDFCmpKind

    source
    pub(all) enum SIMDFCmpKind {
      Eq
      Gt
      Ge
    }

    SIMD floating-point comparison kind

    ShiftType

    source
    pub(all) enum ShiftType {
      Lsl
      Lsr
      Asr
    }

    Shift type for shifted operand instructions
    impl Show for ShiftType

    Terminator

    source
    pub(all) enum Terminator {
      Jump(Int, Array[
    Reg    ])
      Branch(
    Reg    , Int, Int)
      BranchCmp(
    Reg    , 
    Reg    , Cond, Bool, Int, Int)
      BranchZero(
    Reg    , Bool, Bool, Int, Int)
      BranchCmpImm(
    Reg    , Int, Cond, Bool, Int, Int)
      Return(Array[
    Reg    ])
      Trap(Int)
      BrTable(
    Reg    , Array[Int], Int)
    }

    MachV terminator - how a block ends
    impl Show for Terminator

    aarch64_logic_imm_enc_bits

    source
    fn aarch64_logic_imm_enc_bits(value : Int64, is_64 : Bool) -> Int?

    AArch64 logical immediates are encoded as N:immr:imms (1:6:6), placed at bits 22..10.

    is_64 selects whether the encoding is for a 64-bit or 32-bit instruction. For 32-bit, we follow Cranelift: duplicate the low 32 bits into both halves of a u64, then run the same encoder.

    result_classes_for_vregs

    source

    Source Files

    Powered by MoonBit

    Site sourceReport issuePackagesBuild queueSkillsStatistics

    © 2026 mooncakes.io