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pub(all) struct Capacitor {
id : Int
from_node : Int
to_node : Int?
capacitance : Double
span : SourceSpan?
} derive(Debug)pub(all) struct Connection {
node_id : Int
direction : Direction
coordinate : Point?
load_capacitance : Double?
driving_cell : String?
span : SourceSpan?
} derive(Debug)pub(all) struct Design {
header : DesignHeader
name_map : Array[NameMapEntry]
ports : Array[PortDecl]
nets : Array[Net]
} derive(Debug)pub(all) struct DesignHeader {
spef_version : String?
design_name : String?
date : String?
vendor : String?
program : String?
program_version : String?
design_flow : Array[String]
divider : String
delimiter : String
bus_delimiter_open : String
bus_delimiter_close : String
time_unit : UnitScale
capacitance_unit : UnitScale
resistance_unit : UnitScale
inductance_unit : UnitScale
} derive(Debug)pub(all) struct Net {
id : Int
name : String
declared_capacitance : Double
nodes : Array[Node]
connections : Array[Connection]
resistors : Array[Resistor]
capacitors : Array[Capacitor]
span : SourceSpan?
} derive(Debug)pub(all) struct PortDecl {
name : String
direction : Direction
coordinate : Point?
span : SourceSpan?
} derive(Debug)pub(all) struct RCNetwork {
header : DesignHeader
name_map : Array[NameMapEntry]
ports : Array[PortDecl]
nets : Array[Net]
diagnostics : Array[Diagnostic]
} derive(Debug)pub(all) struct Resistor {
id : Int
from_node : Int
to_node : Int
resistance : Double
span : SourceSpan?
} derive(Debug)Install
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