dtzrttp/moonbit-rtl/src/syntax does not have a README file

    AlwaysBlock

    pub(all) struct AlwaysBlock {
    sensitivity : Array[Sensitivity]
    body : Statement
    span :
    Span

    } derive(Eq,
    Debug
    )

    CaseArm

    Connection

    pub(all) struct Connection {
    port_name : String?
    expression : Expression
    span :
    Span

    } derive(Eq,
    Debug
    )

    ContinuousAssign

    pub(all) struct ContinuousAssign {
    target : Expression
    value : Expression
    span :
    Span

    } derive(Eq,
    Debug
    )

    Design

    pub(all) struct Design {
    modules : Array[Module]
    } derive(Eq,
    Debug
    )

    Design::find_module

    fn Design::find_module(self : Design, name : String) -> Module?

    Find a module in a design by name.

    Design::item_count

    fn Design::item_count(self : Design) -> Int

    Count module items across a design.

    Design::metrics

    fn Design::metrics(self : Design) -> DesignMetrics

    Design::module_names

    fn Design::module_names(self : Design) -> Array[String]

    Return module names in declaration order.

    Design::new

    fn Design::new(modules : Array[Module]) -> Design

    DesignMetrics

    pub(all) struct DesignMetrics {
    modules : Int
    ports : Int
    signals : Int
    assignments : Int
    always_blocks : Int
    instances : Int
    expressions : Int
    statements : Int
    maximum_control_depth : Int
    } derive(Eq,
    Debug
    )

    Direction

    pub(all) enum Direction {
    Input
    Output
    Inout
    Unspecified
    } derive(Eq,
    Debug
    )

    EdgeKind

    pub(all) enum EdgeKind {
    Any
    Posedge
    Negedge
    } derive(Eq,
    Debug
    )

    Expression

    Expression::binary

    fn Expression::binary(left : Expression, operator : String, right : Expression, span :
    Span
    ) -> Expression

    Expression::contains_name

    fn Expression::contains_name(self : Expression, wanted : String) -> Bool

    Return whether an expression contains a reference to a name.

    Expression::name

    Expression::name_text

    fn Expression::name_text(self : Expression) -> String?

    Return the referenced name when an expression is a plain name.

    Expression::node_count

    fn Expression::node_count(self : Expression) -> Int

    Count expression nodes in source order.

    Expression::number

    fn Expression::number(value : String, span :
    Span
    ) -> Expression

    Expression::referenced_names

    fn Expression::referenced_names(self : Expression) -> Array[String]

    Expression::string

    fn Expression::string(value : String, span :
    Span
    ) -> Expression

    Instance

    pub(all) struct Instance {
    module_name : String
    instance_name : String
    connections : Array[Connection]
    span :
    Span

    } derive(Eq,
    Debug
    )

    Module

    pub(all) struct Module {
    name : String
    ports : Array[Port]
    signals : Array[Signal]
    items : Array[ModuleItem]
    span :
    Span

    } derive(Eq,
    Debug
    )

    Module::assignment_count

    fn Module::assignment_count(self : Module) -> Int

    Module::find_port

    fn Module::find_port(self : Module, name : String) -> Port?

    Find a port by name without exposing the representation to callers.

    Module::find_signal

    fn Module::find_signal(self : Module, name : String) -> Signal?

    Find a declared signal by name.

    Module::instance_names

    fn Module::instance_names(self : Module) -> Array[String]

    Return instance names in declaration order.

    Module::new

    fn Module::new(name : String, ports : Array[Port], signals : Array[Signal], items : Array[ModuleItem], span :
    Span
    ) -> Module

    Module::port_names

    fn Module::port_names(self : Module) -> Array[String]

    Module::signal_count

    fn Module::signal_count(self : Module) -> Int

    ModuleItem

    pub(all) enum ModuleItem {
    Assign(ContinuousAssign)
    Always(AlwaysBlock)
    Instance(Instance)
    Statement(Statement)
    Unknown(
    Span
    )
    } derive(Eq,
    Debug
    )

    NetType

    pub(all) enum NetType {
    Wire
    Reg
    Logic
    Unspecified
    } derive(Eq,
    Debug
    )

    Port

    pub(all) struct Port {
    name : String
    direction : Direction
    width : Range?
    span :
    Span

    } derive(Eq,
    Debug
    )

    Port::new

    fn Port::new(name : String, direction : Direction, width : Range?, span :
    Span
    ) -> Port

    Range

    pub(all) struct Range {
    msb : Int
    lsb : Int
    span :
    Span

    } derive(Eq,
    Debug
    )

    Range::new

    fn Range::new(msb : Int, lsb : Int, span :
    Span
    ) -> Range

    Range::width

    fn Range::width(self : Range) -> Int?

    Sensitivity

    pub(all) struct Sensitivity {
    edge : EdgeKind
    expression : Expression
    span :
    Span

    } derive(Eq,
    Debug
    )

    Signal

    pub(all) struct Signal {
    name : String
    net_type : NetType
    width : Range?
    span :
    Span

    } derive(Eq,
    Debug
    )

    Signal::new

    fn Signal::new(name : String, net_type : NetType, width : Range?, span :
    Span
    ) -> Signal

    Statement

    Statement::assigned_names

    fn Statement::assigned_names(self : Statement) -> Array[String]

    Statement::control_depth

    fn Statement::control_depth(self : Statement) -> Int

    Statement::node_count

    fn Statement::node_count(self : Statement) -> Int

    Count statements recursively, including block and branch nodes.

    Statement::read_names

    fn Statement::read_names(self : Statement) -> Array[String]

    visit_design

    fn visit_design(design : Design, visit : (String) -> Unit) -> Unit