A practical Verilog RTL parser and rule checker written in MoonBit.
Dependencies
moon update
moon check --deny-warn
moon test --deny-warn
moon run cmd --target native -- --summarymoon run cmd --target native -- --file examples/basic.v --json
moon run cmd --target native -- --benchmark=100 --benchmark-fixture=largelet result = @yzfyzf12345678/moonbit-rtl/src.run_default_pipeline(source)
println(result.status_line())--file PATH read a Verilog source file
--json emit JSON diagnostics
--sarif emit SARIF 2.1.0
--markdown emit a Markdown diagnostic table
--summary print counts and rule IDs
--tokens print tokens with source positions
--disable=RTLxxx disable one rule
--max-diagnostics N cap emitted findings
--benchmark[=N] run the deterministic benchmarksource -> preprocessor -> lexer/parser -> enriched AST
-> checker/width/dataflow/hierarchy/timing/coverage
-> simulation/IR/query/netlist/verification
-> reports, CLI, editor, CI, and release evidencemoon run cmd --target native -- --benchmark=1000moon fmt
moon info
moon check --target all --deny-warn
moon test --target all --deny-warnA practical Verilog RTL parser and rule checker written in MoonBit.
Dependencies